1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to an improved integrated voltage sustainer circuit.
2. Discussion of the Prior Art
As shown in FIG. 1, a conventional voltage sustainer includes two field effect transistors (FETs) 10 and 12 which are sequentially connected, in diode configuration, between a supply voltage V.sub.CC and an output node A. An MOS capacitor 14 has one of its sides connected to receive an input signal .phi.s. The other side of capacitor 14 is connected to the interconnection between the source of transistor 10 and the drain of transistor 12. The input signal .phi.s toggles between OV and V.sub.CC. When the input signal .phi.s goes low, node B in FIG. 1 is precharged to V.sub.CC -VT through transistor 10, where V.sub.T is the threshold voltage of each of the two transistors 10 and 12. When input .phi.s goes high, node B is pumped by capacitor 14 to 2V.sub.CC -V.sub.T. This voltage travels through transistor 12 and sustains node A at 2V.sub.CC -2V.sub.T.
The disadvantage of the conventional voltage sustainer configuration illustrated in FIG. 1 is that if node A goes low, i.e. to ground, than DC current is initiated from the supply V.sub.CC through both transistor 10 and transistor 12 to ground.